I have this part of code which is not synthesizable because the number of times the loop will execute is not definite. I am a beginner with VHDL, how can I convert it to a synthesizable form?Note: I tried doing it with for loop too, along with break statement, but it is still not synthesizable due to the break statement.The code below is to calculate the value of ee such that the greatest common divisor of ee and Phi is 1.
library IEEE;use IEEE.STD_LOGIC_1164.ALL;entity gcd11 isPort ( ee : out integer;Phi : in integer);--gc : out integer);end gcd11;architecture Behavioral of gcd11 issignal rem1,dd,dv,gc,temp: integer;beginprocess(temp,Phi,rem1,dd,dv,gc)begingc<=2;temp<=1;while(gc/=1) looptemp<=temp+1;rem1<=1;if (temp<Phi)thendd<=Phi;dv<=temp;elsif(temp>=Phi) thendd<=temp;dv<=Phi;end if;while(rem1/=0) looprem1<= dd mod dv;dd<=dv;gc<=dv;dv<=rem1;end loop;end loop;ee<=temp;end process;end Behavioral;Best Answer
First of all I would start with reading a book on VHDL as hardware design is very different from software design.
Next to that 3 main this that will not allow you to synthesis:
loops:It's important to understand that a VHDL loop will not iterate like a software loop but is unfolded during synthesis and the resulting logic (all iterations) will run as parallel hardware blocks
Meaning that if you have a for loop that will run 8 times the circuit described will be instantiated 8 times. The follwing loop will create 8 parallel "AND" gates each taking 1 bit input from bus A and 1 bit from signal B.
for I in 0 to 7 loopZ(I) <= A(I) and B;end loop;This means that at the moment you start the logic synthesis the amount of loops needs to be know as hardware can not be added/removed after synthesis.
mod:Modulo function are in general not suited for synthisis. Only if your operands (inputs) are fixed (synthisis can calculate the output upfront) or you you have an statement that resembles the code below your synthesizer will allow it.(mod with a power of 2)
z <= y mod 2**xsignal declartion:In VHDL that need to be synthezised you need to tell the tool how "large" (read: how many bits) a signal is. It is common practice to not use a blunt integer declaration but to use either a std_logic_vector type of an integer of a given range.signal x : std_logic_vector(31 downto 0); signal y : integer range 1 to 31;