I am trying to create a few constants and assign hex numbers to them; however, I keep getting errors.

I want the constant FOO_CONST to be equal to 0x38

Like this...

constant FOO_CONST : integer := x"38";

The error:

Type integer does not match with a string literal

I've tried a few variants with no success.

2

Best Answer


You can specify a base for integers by using the format base#value#:

constant FOO_CONST : integer := 16#38#;

In general, you can use literals in expressions as follows:

Numeric literals may be expressed in any base from 2 to 16. They may also be broken up using underscore, for clarity.

FOO_CONST_HEX <= 16#FF#;FOO_CONST_BIN <= 2#1010_1010#;FOO_CONST_BROKEN := 1_000_000.0; -- breaking the number using _

To answer the question clearly, you can do as Erasmus Cedernaes suggested:

constant FOO_CONST: integer:= 16#38#;

OR

constant FOO_CONST : std_logic_vector := X"38"; -- if you will convert it to a std_logic_vector later

Literals for arrays of characters, such as string, bit_vector and std_logic_vector are placed in double quotes:

constant FLAG :bit_vector(0 to 7) := "11111111";constant MSG : string := "Hello";

Numeric literals with a decimal point are real, those without are integer;

constant FREEZE : integer := 32;constant TEMP : real := 32.0;

Real numbers may be expressed in exponential form:

FACTOR := 2.2E-6;

Literals of type time (and other physical types) must have units. The units should be preceded by a space, although some tools may not require this:

constant DEL1 :time := 10 ns;constant DEL2 :time := 2.27 us;

Literals of enumerated types may either be characters (as for bit and std_logic), or identifiers:

type MY_LOGIC is ('X','0','1','Z');type T_STATE is (IDLE, READ, END_CYC);signal CLK : MY_LOGIC := '0';signal STATE : T_STATE := IDLE;

Bit vector literals may be expressed in binary (default), octal or hex. They may also contain embedded underscores for clarity. These forms may not be used as std_logic_vector literals:

BIT_8_BUS <= B"1111_1111";BIT_9_BUS <= O"353";BIT_16_BUS <= X"AA55";

Notice that:

Literals are supported for synthesis, providing they are of a typeacceptable to the logic synthesis tool. They are either synthesized asconnections to logic '1' or '0' or are used to help minimize thenumber of gates required.

Reference