I have a vector, my_vector, and I want to or each bit with a single bit, my_bit, how can I do this?
In VHDL I would have to write something like:
foo <= (n-1 downto 0 => my_bit) || my_vector;Is there an easier way of doing this in verilog?I tried:
foo = my_bit | my_vector;but it looks like it just does {0...0,my_bit} | my_vector
Best Answer
Are you sure you want to do or? Then you will only have 2 possible outputs: the original vector (if the bit is 0), and a vector of all 1's (if the bit is 1).
If so you can just use this conditional assignment:
assign my_vector = (my_bit == 0) ? my_vector : n'b111...1; One way to do it is:
foo = {n{my_bit}} | my_vector;